The present invention relates generally to memory devices and in particular the present invention relates to a synchronous memory device having FIFO read buffers.
Synchronous memory devices have become the standard for high-speed systems. These systems allow input signals to be presented to the memory devices on a given clock edge and hence reduce the likelihood of asynchronous activities causing bad functionality. One of the above-described memories is a synchronous dynamic random access memory (SDRAM) device, and the functionality of SDRAM devices is well known and understood. Another synchronous memory is a synchronous nonvolatile device called Synchronous Flash that has the same interconnect design as SDRAM and behaves like an SDRAM device for reading. Due to the fact that the synchronous flash is non-volatile, write operations are done differently than an SDRAM. For read operation, however, the synchronous flash has external command timing that is exactly like an SDRAM.
It is perhaps useful to describe the operation of the data read function in more detail. As mentioned above, the reading of the Synchronous flash device is done synchronously, and an active command is presented to the memory on a rising edge of an externally provided clock signal. This command opens up a page of the non-volatile memory array. The page can be different length based on a particular design, such as 4K to 8K bits wide. By opening the page, the device does an internal read of all the memory cells that are placed on that row line or page and stores them in a latch for further access. A Read command and column address are then presented to the memory on a rising edge of the clock three cycles later. The three cycle delay from the active command receipt is required to satisfy a specification of active to read that is about 30 ns on some 100 MHz SDRAM device types, which is the same as the Synchronous flash device.
In general during the read operation, data is retrieved from the active page and presented on output data connections. There is latency relative to the clock of how many cycles of the clock it takes for the device to output the data corresponding to the address of the column that was presented to the part during the read command. After the latency has been satisfied, the memory outputs data. Data may be presented on every consecutive clock edge. Either the data corresponding to further read commands or data in the locations adjacent to the original address in a burst fashion. This is in case the burst length has been set to a number higher than one in an internal mode register. For example, a burst length of eight would require a read command and after the latency (in this case 3) has been satisfied, the memory would output the data corresponding to the column address present on the address bus during the read command and sequentially output the next seven column address locations on the next seven rising edges of the clock.
The prior art architecture that supported such functionality included high speed decoding of the location in the open page or YMUX. A FIFO buffer is provided in series the output path to provide the read latency. For example, in 100 MHz memory devices with a three-clock cycle read latency the FIFO has three stages. This FIFO is typically located next to the output buffers to assist in meeting tight access time specification requirements defined from an edge of the clock signal to when the data appears at the output data connections. Since this is a very difficult specification to satisfy, the memory designers place the FIFO proximate to the output buffer so that once the FIFO opens up the data is presented to the output buffer for immediate and least delay to get to the output connections.
As the speed of the memory devices become faster, the total read delay to decode the column address, output sense amplifier latches to secondary sense amps, and place the data on a general bus to provide the data to the FIFO next to the output buffers is becoming a limiting factor in achieving faster operating speeds.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a methods and circuits to increase the operating read times of synchronous memory devices while providing the required read latency.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a synchronous non-volatile memory device comprises an array of memory cells arranged in columns, sense amplifier circuitry coupled to the columns of the array, and a first FIFO buffer stage coupled to the sense amplifier circuitry. An internal communication line traversing the memory device. A driver circuit is coupled between the first FIFO buffer stage and the internal communication line, and a second FIFO buffer stage located remotely from the first FIFO buffer stage and is coupled to receive an output from the first FIFO buffer stage via the internal communication line.
In another embodiment, a synchronous memory device comprises a differential sense amplifier, a first pass circuit coupled to the differential sense amplifier, a first latch circuit coupled to the first pass circuitry, a second pass circuit coupled to the first latch circuit, and a first FIFO buffer stage coupled to the second pass circuit. A data driver circuit is coupled between the first FIFO buffer stage and an internal data line. The memory comprises a second latch circuit coupled to the internal data line remote from the data driver circuit, a third pass circuit coupled to the second latch circuit, a second FIFO buffer stage coupled to the third pass circuit, a fourth pass circuit coupled to the second latch circuit, and a third FIFO buffer stage coupled to the fourth pass circuit.
A method of operating a synchronous memory device comprises initiating a read operation on a first clock cycle, sensing data stored in a memory cell during the first clock cycle, latching the sensed data during the first clock cycle, and coupling the latched data to a first FIFO buffer stage during the first clock cycle. An output of the first FIFO buffer stage is driven on an internal data line during a second subsequent clock cycle, and the internal data line is coupled to a second FIFO buffer stage during the second clock cycle.